1. Field of the Invention
The present invention relates to phase lock loop circuits and more particularly to preconditioning circuits which enable cheap commercially available phase lock loop circuits to be used with a coded stream of data pulses which do not have a pulse transition during every data cell time.
2. Description of the Prior Art
Heretofore, preconditioning logic circuits and compensating logic circuits have been employed to convert coded data pulses into a usable stream of data pulses before applying them to the input of a phase lock loop circuit. The preconditioning circuit enables the phase lock loop to lock on to the frequency of the data cells of the coded data. Such preconditioning logic circuits have been classified in class 307, subclasses 208 etc.
Preconditioning logic circuits are generally employed when the phase lock loop to be used includes a nonharmonic phase detector and the coded data input stream consists of high density coded data being read from a disk memory or other serial interface. The speed of a disk memory is subject to small variations in frequency such that a fixed frequency oscillator cannot be used to stay synchronized with the stream of coded data pulses. A phase lock loop of the type having a phase detector and a voltage controlled oscillator has been used to track and follow the input stream of coded data pulses so as to synchronize on the stream of data pulses. Heretofore, phase lock loop employing nonharmonic phase detectors would not sychronize with or lock onto a stream of data pulses which did not have data transitions occurring in a predeterminable regular pattern.
There is a problem in synchronizing on the stream of coded data pulses when the input data stream of coded pulses comprises non-repetitive coded data pulses. Such irregular pulses when applied with repetitive an regular clock pulses to a nonharmonic phase detector produces a voltage output which is not representative of the frequency of the data cells. The phase detector generates an out-of-sync signal which causes the voltage controlled oscillator and the phase lock loop to generate pulses out of synchronism with the frequency of the data cells.
High density data codes such as PM, 3PM, MFM, M.sup.2 FM as well as Cohn-Lempel codes, generically known as M for N rate NRZI run bounded codes, are non-repetitive and may have consecutive data cell times in which no transitions occur.
On prior art solution to the problem of driving a phase lock loop with irregular pulses is to employ a logic circuit which senses whether the data pulses are occurring at regular data cell intervals. If the data pulses are regular, they are then fed to a nonharmonic phase detector in a phase lock loop. However, when the logic senses that the coded data pulses are irregular, the circuit logic switches over to a harmonic phase detector for generating pulses approximating the data cell frequency.
Other prior art logic circuits have been suggested in which the phase detector of the phase lock loop is first supplied with a regular series of data pulses having the desired data rate frequency. The voltage level at the input of the phase detector which is representative of the desired data rate is measured and duplicated by a matching circuit. Further logic circuitry senses the absence of repetitive data pulses and the matching voltage is substituted at the input of the phase detector so as to present an output which drives the voltage controlled oscillator of the phase lock loop at a desired predetermined frequency.
U.S. Pat. No. 3,950,658 shows and teaches a compensation circuit which will generate an output clock pulse synchronized with an input data stream of MFM coded data. This reference employs a charge pump which includes a pair of capacitors. The charge on the two capacitors are employed to generate a correction voltage representative of a difference between the data time frequency and the clock time frequency. This reference also explains that prior art attempts to generate clock pulses from a modified frequency modulation (MFM) raw data signal introduced errors in the voltage controlled oscillator when a data pulse was either early or late. It is known that delay circuits and logic gating circuits which compare the length of data pulses with clock pulses and/or compare the leading or trailing edges of data pulses with clock pulses will generate error signals when the data pulse is distorted or arrives either early or late.